Dynamic random access memory (DRAM) circuits are used in the electronics industry for storing information as binary data. A DRAM typically comprises millions of memory cells tightly packed in an array on a semiconductor substrate. Each of the memory cells typically includes an access transistor and a storage capacitor, and the cells are accessed using word lines and bit lines. In order to increase the density of the memory cells, the footprint of, or area occupied by, each memory cell typically should be decreased. One difficulty in reducing the area of a memory cell is that when the surface area of the capacitor storage nodes becomes too small, the capacitor cannot store a sufficient amount of electric charge, for a sufficient amount of time. Data is thus often lost due to leakage current.
Various storage capacitor and transistor structures have been proposed that occupy a relatively small area on the semiconductor substrate. For example, vertical trench capacitors have been developed that extend deep into the substrate so that the capacitor occupies less area on the surface of the substrate, yet its storage node has enough surface area in the depth direction of the substrate to retain sufficient electric charge. DRAM cells including trench capacitors thus have comparatively large capacitance while occupying a comparatively small area on a semiconductor chip surface. In particular, trench capacitors are characterized by deep and narrow trenches in the semiconductor substrate. An insulator formed on the trench walls serves as the capacitor dielectric. Capacitor plates are formed on either side of the insulator, and one of the plates is formed by refilling the trench with doped polysilicon. Typically, a horizontal field effect transistor (FET) is coupled to the trench capacitor on and in the surface of the semiconductor substrate.
In recent years, cell density has increased dramatically on the DRAM chip because of improvements in semiconductor technologies. As DRAM technology progresses, the number of memory cells on a DRAM chip, each storing a bit of information, is expected to exceed several gigabits. As this cell density increases on the chip, it is necessary to reduce the area of each cell, while at the same time improving circuit performance.
Unfortunately, as the cell size decreases, the size of the storage capacitor and cell area are often also reduced. This results in decreased charge stored on the capacitor, which, in turn, makes detection of stored charge during the read cycle more difficult due to a lower signal-to-noise ratio at the read-sense amplifiers. The cells also require more frequent refresh cycles to maintain sufficient charge on the capacitor. In addition, as cell size decreases, the capacitor is more susceptible to the effects of leakage current, which affects the capacitor's ability to retain stored electrical charge. Therefore, there is a strong need to improve the retention time of the storage capacitor while reducing the cell area.
Improvement of retention time is a key issue for realizing future high-density DRAMs, because the required retention time is a factor that doubles with each successive DRAM generation (e.g. 256 mbit—512 mbit—1 gbit, etc.). The duration of the retention time is derived from the need to keep the capacitor refresh interval constant as the number of bits increases. Two major approaches to enhance retention characteristics are therefore (i) improving the cell to bit-line capacitance ratio and (ii) suppressing leakage current.
To improve the cell to bit-line capacitance ratio, much attention has been directed to the use of high-k dielectrics in the cell capacitors. Implementation of most high-k dielectrics, however, requires the use of new semiconductor tools, such as Atomic Layer Deposition (ALD) Chemical Vapor Deposition (CVD). Without employing new semiconductor tools, however, others have increased cell capacitance by increasing the nitridation of an existent capacitor nitrogen-oxide (NO) dielectric layer. The nitridation, however, results in a higher leakage current, which degrades the capacitor charge retention characteristics.
The depth of the doped polysilicon plate recess in the trench can be reduced, thereby making a larger NO dielectric layer in the trench. Unfortunately, continuous decreasing of the doped polysilicon plate recess depth inevitably induces increased leakage current from a vertical parasitic metal-oxide-semiconductor (MOS) FET (MOSFET).
To reduce leakage current, much attention has been given to embedding silicon-on-insulator (SOI) technology in the trench region by implanting oxygen in an upper portion of the trench (e.g., the collar region), coupled with a subsequent annealing treatment. With this approach, the collar oxide is thickened, effectively increasing the thickness of a “gate” oxide in the parasitic MOSFET just discussed, thereby reducing leakage current. Although this approach could curb some amount of leakage current, the leakage current contributed by the junction between a FET and the polysilicon plate through the collar oxide still cannot be suppressed. This leakage is regarded as the most critical leakage path, because it detrimentally impacts retention performance in the current state-of-the-art D11 double-data-rate-2 (D11 DDR2) DRAM memory.
The present invention is directed to overcome one or more of the problems of the prior art.